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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT573 Octal D-type transparent latch; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state FEATURES * Inputs and outputs on opposite sides of package allowing easy interface with microprocessors * Useful as input or output port for microprocessors/microcomputers * 3-state non-inverting outputs for bus oriented applications * Common 3-state output enable input * Functionally identical to the "563" and "373" * Output capability: bus driver * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT573 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches. The "573" consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns 74HC/HCT573 the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. The "573" is functionally identical to the "563" and "373", but the "563" has inverted outputs and the "373" has a different pin arrangement. TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay Dn to Qn LE to Qn CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF; VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". input capacitance power dissipation capacitance per latch notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 14 15 3.5 26 17 15 3.5 26 ns ns pF pF HCT UNIT December 1990 2 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state PIN DESCRIPTION PIN NO. 2, 3, 4, 5, 6, 7, 8, 9 11 1 10 19, 18, 17, 16, 15, 14, 13, 12 20 SYMBOL D0 to D7 LE OE GND Q0 to Q7 VCC NAME AND FUNCTION data inputs latch enable input (active HIGH) 74HC/HCT573 3-state output enable input (active LOW) ground (0 V) 3-state latch outputs positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state FUNCTION TABLE OPERATING MODES enable and read register (transparent mode) latch and read register latch register and disable outputs Notes INPUTS OE L L L L H H LE H H L L L L DN L H l h l h 74HC/HCT573 INTERNAL LATCHES L H L H L H OUTPUTS Q0 to Q7 L H L H Z Z 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition Z = high impedance OFF-state Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. tPHL/ tPLH propagation delay Dn to Qn propagation delay LE to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time typ. 47 17 14 50 18 14 44 16 13 55 20 16 14 5 4 80 16 14 50 10 9 5 5 5 14 5 4 11 4 3 3 1 1 max. 150 30 26 150 30 26 140 28 24 150 30 26 60 12 10 100 20 17 65 13 11 5 5 5 -40 to +85 min. max. 190 38 33 190 38 33 175 35 30 190 38 33 75 15 13 120 24 20 75 15 13 5 5 5 -40 to +125 min. max. 225 45 38 225 45 38 210 42 36 225 45 38 90 18 15 ns 74HC/HCT573 TEST CONDITIONS UNIT V CC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 tPHL/ tPLH ns Fig.7 tPZH/ tPZL ns Fig.8 tPHZ/ tPLZ ns Fig.8 tTHL/ tTLH ns Fig.6 tW enable pulse width HIGH set-up time Dn to LE hold time Dn to LE ns Fig.7 tsu ns Fig.9 th ns Fig.9 December 1990 5 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI Note to HCT types 74HC/HCT573 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT Dn LE OE UNIT LOAD COEFFICIENT 0.35 0.65 1.25 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 min. tPHL/ tPLH tPHL/ tPLH tPZH/ tPZL propagation delay Dn to Qn propagation delay LE to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time enable pulse width HIGH set-up time Dn to LE hold time Dn to LE 16 13 9 typ. 20 18 17 max. 35 35 30 -40 to +85 min. max. 44 44 38 -40 to +125 min. max. 53 53 45 ns ns ns 4.5 4.5 4.5 Fig.6 Fig.7 Fig.8 UNIT V CC WAVEFORMS (V) TEST CONDITIONS tPHZ/ tPLZ 18 30 38 45 ns 4.5 Fig.8 tTHL/ tTLH tW tsu th 5 5 7 4 12 20 16 11 15 24 20 14 18 ns ns ns ns 4.5 4.5 4.5 4.5 Fig.6 Fig.7 Fig.9 Fig.9 December 1990 6 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state AC WAVEFORMS 74HC/HCT573 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the data input (Dn) to output (Qn) propagation delays and the output transition times. Fig.7 Waveforms showing the latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays and the output transition times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the data set-up and hold times for Dn input to LE input. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". Fig.8 Waveforms showing the 3-state enable and disable times. December 1990 7 |
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